Technical Description
This technology presents an asymmetric transistor with a fin-trimming process integrated into CMOS technology, eliminating additional masking through dielectric deposition.
Problems Addressed
- Increased Manufacturing Cost
- Extra Mask Requirement
- Limited CMOS Integration
- Higher Contact Resistance
- Complex Fabrication Process
- Process Variation Challenges
Tech Features
- Enhanced Gate Control
- Efficient CMOS Integration
- Optimized Capacitance Reduction
- Selective Fin-Trimming
- Advanced Asymmetric Channel
- Cost-Effective Fabrication
Target Audience
- Semiconductor & Electronics Industry
- Manufacturing & Fabrication Industry
- Nanoelectronics & Advanced Materials Sector
- Telecommunications & Computing Sector
- Academic & Research Institutions
Tech ID: P16-1362 TRL 4 Patent Status: Published Available For Exclusive and Non-exclusive License
