Asymmetric Fin Field Effect Transistor
Tech ID
P16-1362
Patent Status
Published in India
Design Status
--
Technical Description
This technology presents an asymmetric transistor with a fin-trimming process integrated into CMOS technology, eliminating additional masking through dielectric deposition.
Problems Addressed
- Increased Manufacturing Cost
- Extra Mask Requirement
- Limited CMOS Integration
- Higher Contact Resistance
- Complex Fabrication Process
- Process Variation Challenges
TARGET AUDIENCE
- Semiconductor & Electronics Industry
- Manufacturing & Fabrication Industry
- Nanoelectronics & Advanced Materials Sector
- Telecommunications & Computing Sector
- Academic & Research Institutions
TECH FEATURES
- Enhanced Gate Control
- Efficient CMOS Integration
- Optimized Capacitance Reduction
- Selective Fin-Trimming
- Advanced Asymmetric Channel
- Cost-Effective Fabrication
P16-1362
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Available For
Available for exclusive and non exclusive license
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Cost
—
Stage of Developments
Technology Validated
Contact Person
Mr. Lalit Ambastha
IP Bazzaar Technology Pvt. Ltd.
IP Bazzaar Technology Pvt. Ltd.
12 First Floor, National Park, Lajpat Nagar-IV,
New Delhi-110024, India
Tel: [+91] 11-26360036;
Fax: [+91] 11-26360037;
Mobile: [+91]9811367838;
Email: tech@ipbazzaar.com;
www.ipbazzaar.com
New Delhi-110024, India
Tel: [+91] 11-26360036;
Fax: [+91] 11-26360037;
Mobile: [+91]9811367838;
Email: tech@ipbazzaar.com;
www.ipbazzaar.com