Technical Description
The invention relates to a method of patterning of wafer scale reduced graphene oxide films using CMOS compatible technology on Si/SiO2 substrate.
Problems Addressed
- Complex Method
- Limited Patterning Efficacy
- Narrow Application Range
- Inefficient Methods
Tech Features
- Photolithographic Patterning
- No Film Quality Degradation
- Ambipolar Charge Transport
- Wide Range of Application
- Efficient Technology
- High Throughput
Target Audience
- Semiconductor Industry
- Energy & Power Sector
- Consumer Electronics Industry
- Research & Development
Tech ID: P18-1745 TRL 5 Patent Status: Granted Available For Exclusive and Non-exclusive License
