Technical Description
This technology is a junctionless accumulation-mode ferroelectric synaptic transistor for synaptic weights that ensures zero process overhead and compatibility with pristine FinFET process flow.
Problems Addressed
- Lacks Integration Efficiency
- Lacks SOI Compatibility
- Lacks Conductance Enhancement
- Fails Non-volatile Support
- Inefficient Process Integration
- Lacks Synaptic Performance
- Fails FinFet Compatibility
- Lacks Memory Functionality
Tech Features
- Efficient Conductance Variation
- Zero Process Overhead
- FinFET Compatible Fabrication
- Masking Enabled Process Flow
- Low Operating Voltage
- Enhanced SOI Compatibility
- Efficient HZO Integration
- Improved Synaptic Weighting
Target Audience
- Semiconductor Manufacturers
- Neuromorphic Hardware Developers
- Chip Foundries And Fabrication Labs
- AI Hardware Accelerator Companies
- Academic & Research Institutions
Tech ID: P16-1466 TRL 4 Patent Status: Published Available For Exclusive and Non-exclusive License
