Technical Description
The technology relates to a thin film transistor having a gate interface between a gate insulating layer and gate electrode to improve the properties of transistors.
Problems Addressed
- High operating voltage
- Not used in low power Devices
- Low dielectric constant
- High Interface Trap Density
Tech Features
- Low Operating Voltage
- Better Electron Mobility
- Lower Subthreshold Swing
- Lower Interface Trap Density
- Manganese (III) Oxide Interface Layer
Target Audience
- Semiconductor Industry
- Consumer Electronics Industry
- Research and Development
Tech ID: P16-1238 TRL 5 Patent Status: Granted Available For Exclusive and Non-exclusive License
