Technical Description
The present invention relates to a system for continuous time pipelined analog-to-digital converter with implicit decimation which provides computational power savings.
Problems Addressed
- Limitations of Existing Methods
- Aliasing Errors
- Complex Design
- Multi-Component System
- Power Loss
Tech Features
- Simple Design
- Reduced Power Dissipation
- Minimized Resolution
- Compact
- Anti-aliasing
- Easy to Drive
- Reliable
- Minimal Components
Target Audience
- Telecommunications Industry
- Automotive Industry
- Consumer Electronics Sector
- Research & Development
Tech ID: P11-1718 TRL 3 Patent Status: Granted Available For Exclusive and Non-exclusive License
